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Published at November 18

SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators

cs.AR

Released Date: November 18, 2024

Authors: Giovanni Brignone¹, Roberto Bosio¹, Fabrizio Ottati¹, Claudio Sansoè¹, Luciano Lavagno¹

Aff.: ¹Politecnico di Torino, Italy

Arxiv: http://arxiv.org/abs/2411.11384v1

Refer to caption

	Ops/Unit ( $\mathrm{1}$ )		DSP ( $\mathrm{1}$ )			Logic LUT ( $\mathrm{k}$ )			Mem. LUT ( $\mathrm{k}$ )			FF ( $\mathrm{k}$ )			Power ( $\mathrm{mW}$ )			$\mathbf{F_{clk}^{max}}$ ( $\mathrm{MHz}$ )
Bench.	BD,BU	S	BD	BU	S	BD	BU	S	BD	BU	S	BD	BU	S	BD	BU	S	BD	BU	S
vadd (Xilinx, 2024b)	$1.00$	$3.40$	$68$	$0$	$20$	$3.49$	$3.53$	$3.30$	$0.59$	$0.59$	$0.59$	$7.80$	$8.18$	$7.29$	$365$	$359$	$345$	$475$	$475$	$425$
SNN (Ottati, 2024)	$1.00$	$3.19$	$150$	$0$	$47$	$1.47$	$2.05$	$1.19$	$0.00$	$0.00$	$0.05$	$2.72$	$3.85$	$2.95$	$439$	$352$	$373$	$450$	$600$	$450$
N. gmean	1.00	3.29	1.00	0.00	0.30	1.00	1.19	0.87	1.00	1.00	7.07	1.00	1.22	1.01	1.00	0.89	0.90	1.0	1.15	0.95