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Published at November 12

Bayes2IMC: In-Memory Computing for Bayesian Binary Neural Networks

cs.ET

cs.AR

Released Date: November 12, 2024

Authors: Prabodh Katti, Clement Ruah, Osvaldo Simeone, Bashir M. Al-Hashimi, Bipin Rajendran

Arxiv: http://arxiv.org/abs/2411.07902v1

Refer to caption

	Units	PCM	SRAM
Clock Rate	MHz	100	208
Ops/clk pulse ( $8/4/2$ )	-	16/32/64	128
Read power per weight	$\mu$ W	48.5	1993
Total read power	mW	6.2	256
Total digital block power ( $8/4/2$ )	mW	1.46/2.92/5.84	26.6
Total power( $8/4/2$ )	mW	7.6/9.1/12.0	282
Total core area	mm²	0.015	0.14
Total sensing block area	mm²	0.02	0.04
Total digital block area	mm²	0.18	0.2
Total BN memory area	mm²	0.002	0.007
Total area	mm²	0.22	0.40
Power efficiency ( $8/4/2$ )	GOPS/W	208/350/531	94.6
Total efficiency ( $8/4/2$ )	GOPS/W/mm²	941/1581/2397	250