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Published at November 10

AMAZE: Accelerated MiMC Hardware Architecture for Zero-Knowledge Applications on the Edge

cs.CR

cs.AR

Released Date: November 10, 2024

Authors: Anees Ahmed¹, Nojan Sheybani², Davi Moreno¹, Nges Brian Njungle¹, Tengkai Gong², Michel Kinsy¹, Farinaz Koushanfar²

Aff.: ¹Arizona State University; ²University of California San Diego

Arxiv: http://arxiv.org/abs/2411.06350v1

Refer to caption

		Resource Utilization					Timing
	Batch						Total		Amortized	Amortized
Design	size	ALMs	LUTs	FFs	BRAM (bits)	DSPs	Cycles	Freq. (MHz)	Latency (µs)	Throughput (ops/s)	Power (W)
AMZ-1	13	20,011 (13%)	41,227 (13%)	24,623 (4%)	1,386 (1%)	226 (89%)	4,823	128.27	2.892	345,781	2.753
AMZ-1a	4	21,898 (14%)	43,025 (14%)	6,201 (1%)	0 (0%)	228 (89%)	1,547	43.47	8.896	112,410	10.722
AMZ-1b	1	21,449 (14%)	42,120 (14%)	4,964 (1%)	0 (0%)	228 (89%)	4,189	44.89	93.316	10,716	9.579
AMZ-2	13	59,765 (38%)	120,118 (38%)	56,660 (9%)	2,772 (1%)	218 (86%)	3,640	125.75	2.226	449,236	3.807
AMZ-2a	4	68,933 (43%)	133,866 (42%)	7,389 (2%)	0 (0%)	224 (88%)	1,183	39.97	7.399	135,153	11.508
AMZ-2b	1	68,236 (43%)	133,816 (42%)	17,687 (3%)	0 (0%)	224 (88%)	3,370	44.07	76.469	13,077	12.185
AMZ-3	1	4,514 (3%)	7,391 (3%)	5,518 (1%)	0 (0%)	0 (0%)	72,028	151.45	475.589	2,102	1.176