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Published at November 13

A System Level Performance Evaluation for Superconducting Digital Systems

cs.AR

cs.AI

cs.ET

Released Date: November 13, 2024

Authors: Joyjit Kundu¹, Debjyoti Bhattacharjee¹, Nathan Josephsen¹, Ankit Pokhrel¹, Udara De Silva¹, Wenzhe Guo¹, Steven Van Winckel¹, Steven Brebels¹, Manu Perumkunnil¹, Quentin Herr¹, Anna Herr¹

Aff.: ¹IMEC

Arxiv: http://arxiv.org/abs/2411.08645v1

Parameter	CMOS 5nm	This work
Operating Frequency	2GHz	30GHz
Device	FinFET	Josephson Junction
– Device Density	$\sim 170M/mm^{2}$	$\sim 4M/mm^{2}$
– Voltage	$0.7V$	$\sim$ 1.0mV
On-chip Memory	SRAM	JSRAM
– Density (incl. peri)	$\sim$ $4.5MB/mm^{2}$	$\sim$ $0.4M/mm^{2}$
– HD Device Unit Cell	6T	8JJ
(Single Port 1R/1W)	$0.021\mu$ $m^{2}$	$1.86\mu$ $m^{2}$
Lithography	EUV	193
ML stack layers	16	16
Interconnects	Cu	NbTiN
– Resisitivity (M1-M3)	$\sim$ 75 $\mu$ $\Omega$ .m	$<$ 2 $\mu$ $\Omega$ .m
– Minimum MP	28nm/35nm	50nm
– Power Efficiency	1-2Gb@1pJ/bit	$\sim$ 200Gb@1pJ/bit